SH7670 Datasheet, PDF (922/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.5 Memory Map
Table 20.3 shows the memory map of HIFRAM.
Table 20.3 Memory Map
Classification
Start Address
End Address
Memory Size
Map from external device*¹
H'0000
H'07FF
2 kbytes
Map from on-chip CPU*¹ *²
H'FFFF_F000
H'FFFF_F7FF
2 kbytes
Notes: 1. Map for a single HIFRAM bank. Which bank is to be accessed by an external device or
the on-chip CPU depends on the BMD and BSEL bits in HIFSCR. The mapping
addresses are common between the banks.
2. In HIF boot mode, however, bank 0 is selected and the first 2 kbytes of the first-half 32
Mbytes in the following areas are also mapped: (1) the cacheable area 0 in the
H'0000_0000 to H'0000_07FF range and (2) the non-cacheable area 0 in the
H'2000_0000 to H'2000_07FF range.
If an external device modifies HIFRAM when HIFRAM is accessed from the cacheable
area with the cache enabled, a coherency problem will occur. When the cache is
enabled, accessing HIFRAM from the non-cacheable area is recommended.
In HIF boot mode, among the first-half 32 Mbytes of each area 0, access to only the
addresses to which HIFRAM is mapped is permitted.
Even in HIF boot mode, the areas excluding the first-half 32 Mbytes of area 0 are
mapped to the external memory as normally.
Rev. 1.00 Nov. 14, 2007 Page 896 of 1262
REJ09B0437-0100