SH7670 Datasheet, PDF (691/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
17.3.10 Interrupts Enable Register 0 (INTENB0)
INTENB0 is a register that specifies the various interrupt masks. On detecting the interrupt
corresponding to the bit in this register to which software has set 1, this module generates the USB
interrupt.
This module sets 1 to each status bit in INTSTS0 when a detection condition of the corresponding
interrupt source has been satisfied regardless of the set value in INTENB0 (regardless of whether
the interrupt output is enabled or disabled).
While the status bit in INTSTS0 corresponding to the interrupt source indicates 1, this module
generates the USB interrupt when software modifies the corresponding interrupt enable bit in
INTENB0 from 0 to 1.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Initial
Bit
Bit Name
Value R/W Description
15
VBSE
0
R/W VBUS Interrupts Enable
Enables or disables the USB interrupt output when
the VBINT interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
14
RSME
0
R/W Resume Interrupts Enable
Enables or disables the USB interrupt output when
the RESM interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 1.00 Nov. 14, 2007 Page 665 of 1262
REJ09B0437-0100