SH7670 Datasheet, PDF (157/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 6 Interrupt Controller (INTC)
Section 6 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
6.1 Features
• 16 levels of interrupt priority can be set
By setting the nine interrupt priority registers, the priorities of IRQ interrupts, and on-chip
peripheral module interrupts can be selected from 16 levels for request sources.
• NMI noise canceler function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as the noise
canceler function.
• Register banks
This LSI has register banks that enable register saving and restoration required in the interrupt
processing to be performed at high speed.
Rev. 1.00 Nov. 14, 2007 Page 131 of 1262
REJ09B0437-0100