SH7670 Datasheet, PDF (494/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.23 Checksum Monitor Register (CSSMR)
CSSMR is a 32-bit read-only register that stores the value of a checksum during the processing of
received packets in E-DMAC. The checksum value can be recognized by monitoring the value
displayed by this register. Note that the value of the data received by E-DMAC may be different
from the checksum value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CS[15:0]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name value R/W Description
31 to 16 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
15 to 0 CS[15:0] 0
R
Checksum Value
These bits can only be read. Writing is prohibited.
These bits are initialized to 0 at the beginning of a
receive packet.
Note * The value is valid only when CSEBL = 1 and CSMD = 0.
Rev. 1.00 Nov. 14, 2007 Page 468 of 1262
REJ09B0437-0100