SH7670 Datasheet, PDF (530/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
Bit Name
8
C[i]I_LI
7 to 1 —
0
C[i]I_EI
Initial
Value R/W
0
R/W
All 0 R
0
R/W
Description
"Continuous Data Last Descriptor Processing End"
Interrupt Request (interrupt request to notify you that
processing described in the descriptor where C[i]F2
is set to 1 ended)
This bit is cleared to 0 by writing 1 to it. When 0 is
written to this bit, the current state is retained.
0: The "last descriptor processing end" interrupt is
not requested.
1: The "last descriptor processing end" interrupt is
requested.
Reserved
These bits are always read as 0. The write value
should always be 0.
"Processing End" Interrupt Request
This bit indicates whether the "processing end"
interrupt is requested.
This bit is cleared to 0 by writing 1 to it. When 0 is
written to this bit, the current state is retained.
0: The "processing end" interrupt is not requested.
1: The "processing end" interrupt is requested.
"Processing end" means fetching of depleted
descriptors (invalid descriptors (descriptors where
C[i]F0 is set to 0)).
Rev. 1.00 Nov. 14, 2007 Page 504 of 1262
REJ09B0437-0100