SH7670 Datasheet, PDF (491/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.20 Transmit Interrupt Register (TRIMD)
TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back
completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0















TIS
Initial Value: ⁰
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/
R
R
R
R
R
R
R
R
R R/W
Bit
Bit Name
31 to 1 
0
TIS
Initial
value
All 0
0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Interrupt Setting
0: Write-back completion for each frame is not notified
1: Write-backed completion for each frame using the
TWB bit in EESR is notified
13.2.21 Checksum Mode Register (CSMR)
CSMR is a 32-bit readable/writable register that specifies the checksum operating mode. Set this
register when reception is stopped.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSEBL CSMD 













Initial Value: 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
R
R
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0










SB[5:0]
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 14, 2007 Page 465 of 1262
REJ09B0437-0100