SH7670 Datasheet, PDF (391/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 10 Watchdog Timer (WDT)
Bit
5
4, 3
2 to 0
Bit Name
TME
Initial
Value
0

All 1
CKS[2:0] 000
R/W Description
R/W Timer Enable
Starts and stops timer operation. Clear this bit to 0
when using the WDT in software standby mode or
when changing the clock frequency.
0: Timer disabled
Count-up stops and WTCNT value is retained
1: Timer enabled
R
Reserved
These bits are always read as 1. The write value
should always be 1.
R/W Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is
shown inside the parenthesis in the table is the value
when the peripheral clock (Pφ) is 25 MHz.
Bits 2 to 0
Clock Ratio Overflow Cycle
000:
1 × Pφ
10.2 µs
001:
1/64 × Pφ
655.4 µs
010:
1/128 × Pφ
1.3 ms
011:
1/256 × Pφ
2.6 ms
100:
1/512 × Pφ
5.2 ms
101:
1/1024 × Pφ 10.5 ms
110:
1/4096 × Pφ 41.9 ms
111:
1/16384 × Pφ 167.8 ms
Note: If the CKS2 to CKS0 bits are modified when
the WDT is running, the counting-up may not
be performed correctly. Ensure that these bits
are modified only when the WDT is not
running.
Rev. 1.00 Nov. 14, 2007 Page 365 of 1262
REJ09B0437-0100