SH7670 Datasheet, PDF (802/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
(3) BEMP Interrupt
On generating the BEMP interrupt for the pipe whose PID bits are set to BUF by software, this
module sets the corresponding PIPEBEMP bit in BEMPSTS to 1. If the corresponding bit in
BEMPENB is set to 1 by software, this module sets the BEMP bit in INTSTS0 to 1, allowing the
USB interrupt to be generated.
The following describes the conditions on which this module generates the internal BEMP
interrupt request.
(a) For the pipe in the transmitting direction, when the FIFO buffer of the corresponding pipe is
empty on completion of transmission (including zero-length packet transmission). In single
buffer mode, the internal BEMP interrupt request is generated simultaneously with the
BRDY interrupt for the pipe other than DCP. However, the internal BEMP interrupt request
is not generated on any of the following conditions.
 When software (DMAC) has already started writing data to the FIFO buffer of the CPU on
completion of transmitting data of one plane in double buffer mode.
 When the buffer is cleared (emptied) by setting the ACLRM or BCLR bit to 1.
 When IN transfer (zero-length packet transmission) is performed during the control transfer
status stage in function controller mode.
(b) For the pipe in the receiving direction:
When the successfully-received data packet size exceeds the specified maximum packet size.
In this case, this module generates the BEMP interrupt request, setting the corresponding
PIPEBEMP bit to 1, and discards the received data and modifies the setting of the PID bits of
the corresponding pipe to STALL (11).
Here, this module returns no response when used as the host controller, and returns STALL
response when used as the function controller.
However, the internal BEMP interrupt request is not generated on any of the following
conditions.
 When a CRC error or bit stuffing error is detected in the received data.
 When a setup transaction is being performed.Writing 0 to the PIPEBEMP bit clears the
status; writing 1 to the PIPEBEMP bit has no effect.
Rev. 1.00 Nov. 14, 2007 Page 776 of 1262
REJ09B0437-0100