SH7670 Datasheet, PDF (13/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

7.4.10 Sequence to Write to ACSWR.......................................................................... 214
7.4.11 Internal Bus Master Bus Priority Register (IBMPR) ........................................ 215
7.5 Operation .......................................................................................................................... 217
7.5.1 Endian/Access Size and Data Alignment.......................................................... 217
7.5.2 Normal Space Interface..................................................................................... 224
7.5.3
7.5.4
Access Wait Control ......................................................................................... 229
CSn Assert Period Expansion ........................................................................... 231
7.5.5 SDRAM Interface ............................................................................................. 232
7.5.6 SRAM Interface with Byte Selection................................................................ 272
7.5.7 PCMCIA Interface ............................................................................................ 277
7.5.8 Wait between Access Cycles ............................................................................ 284
7.5.9 Others................................................................................................................ 290
Section 8 Direct Memory Access Controller (DMAC) .....................................293
8.1 Features............................................................................................................................. 293
8.2 Input/Output Pins.............................................................................................................. 296
8.3 Register Descriptions........................................................................................................ 297
8.3.1 DMA Source Address Registers (SAR)............................................................ 301
8.3.2 DMA Destination Address Registers (DAR).................................................... 302
8.3.3 DMA Transfer Count Registers (DMATCR) ................................................... 302
8.3.4 DMA Channel Control Registers (CHCR) ....................................................... 303
8.3.5 DMA Reload Source Address Registers (RSAR) ............................................. 312
8.3.6 DMA Reload Destination Address Registers (RDAR) ..................................... 313
8.3.7 DMA Reload Transfer Count Registers (RDMATCR)..................................... 314
8.3.8 DMA Operation Register (DMAOR) ............................................................... 315
8.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).............. 319
8.4 Operation .......................................................................................................................... 321
8.4.1 Transfer Flow.................................................................................................... 321
8.4.2 DMA Transfer Requests ................................................................................... 323
8.4.3 Channel Priority................................................................................................ 327
8.4.4 DMA Transfer Types........................................................................................ 330
8.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 339
Section 9 Clock Pulse Generator (CPG)............................................................343
9.1 Features............................................................................................................................. 343
9.2 Input/Output Pins.............................................................................................................. 347
9.3 Clock Operating Modes .................................................................................................... 349
9.4 Register Descriptions........................................................................................................ 354
9.4.1 Frequency Control Register (FRQCR).............................................................. 354
9.5 Changing the Frequency ................................................................................................... 357
Rev. 1.00 Nov. 14, 2007 Page xiii of xxvi