SH7670 Datasheet, PDF (583/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
Initial
Bit
Bit Name Value R/W Description
4
RCVE2 0
R/W Enables or disables RCVF2 interrupt requests.
0: RCVF2 interrupt requests are disabled.
1: RCVF2 interrupt requests are enabled.
3
RCVE1 0
R/W Enables or disables RCVF1 interrupt requests.
0: RCVF1 interrupt requests are disabled.
1: RCVF1 interrupt requests are enabled.
2
UPE
0
R/W Enables or disables UPF interrupt requests.
0: UPF interrupt requests are disabled.
1: UPF interrupt requests are enabled.
1
OPE
0
R/W Enables or disables OPF interrupt requests.
0: OPF interrupt requests are disabled.
1: OPF interrupt requests are enabled.
0
OVE
0
R/W Enables or disables OVF interrupt requests.
0: OVF interrupt requests are disabled.
1: OVF interrupt requests are enabled.
15.3.7 STIF Transfer Size Register (STSIZER) (n = 0,1)
STSIZER is a 32-bit register that specifies a transfer byte count for PS mode. STSIZER is
initialized to H'FFFFFFFF by a power-on reset.
Bit
Bit Name
31 to 0 SIZE31 to
SIZE0
Initial
Value R/W Description
All 1 R/W Transfer byte count for PS mode
Rev. 1.00 Nov. 14, 2007 Page 557 of 1262
REJ09B0437-0100