SH7670 Datasheet, PDF (495/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.3 Operation
The E-DMAC is connected to the EtherC, and performs efficient transfer of transmit/receive data
between the EtherC and memory (buffers) without the intervention of the CPU. The E-DMAC
itself reads control information, including buffer pointers called descriptors, relating to the buffers.
The E-DMAC reads transmit data from the transmit buffer and writes receive data to the receive
buffer in accordance with this control information. By setting up a number of consecutive
descriptors (a descriptor list), it is possible to execute transmission and reception continuously.
13.3.1 Descriptor List and Data Buffers
Before starting transmission/reception, the communication program creates transmit and receive
descriptor lists in memory. The start addresses of these lists are then set in the transmit and receive
descriptor list start address registers.
The descriptor start address must be aligned so that it matches the address boundary according to
the descriptor length set by the E-DMAC mode register (EDMR). The transmit buffer start address
can be aligned with a byte, a word, and a longword boundary.
(1) Transmit Descriptor
Figure 13.2 shows the relationship between a transmit descriptor and the transmit buffer.
According to the specification in this descriptor, the relationship between the transmit frame and
transmit buffer can be defined as one frame/one buffer or one frame/multi-buffer.
Rev. 1.00 Nov. 14, 2007 Page 469 of 1262
REJ09B0437-0100