SH7670 Datasheet, PDF (466/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit
5
4
3 to 1
0
Bit Name
DL1
DL0
Initial
value
0
0

All 0
SWR
0
R/W Description
R/W Descriptor Length
R/W These bits specify the descriptor length.
00: 16 bytes
01: 32 bytes
10: 64 bytes
11: Reserved (setting prohibited)
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Software Reset
Writing 1 in this bit initializes registers of the E-DMAC
other than TDLAR, RDLAR, and RMFCR and registers
of the EtherC. While a software reset is being
executed (64 cycles of the internal bus clock Bφ),
accesses to the all Ethernet-related registers are
prohibited.
Software reset period (example):
When Bφ = 100 MHz: 0.64 µS
When Bφ = 75 MHz: 0.85 µS
This bit is always read as 0.
0: Writing 0 is ignored (E-DMAC operation is not
affected)
1: Writing 1 resets the EtherC and E-DMAC and then
automatically cleared
Rev. 1.00 Nov. 14, 2007 Page 440 of 1262
REJ09B0437-0100