SH7670 Datasheet, PDF (732/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
13
CSCLR
12
CSSTS
Initial
Value
0
0
R/W
R/W*¹
R
Description
C-SPLIT Status Clear for Split Transaction
When the host controller function is selected,
setting this bit to 1 clears the CSSTS bit to 0 for the
transfer using the split transaction. In this case, the
next DCP transfer restarts with the S-SPLIT.
0: Invalid
1: Clears the CSSTS bit to 0.
When software sets this bit to 1, this module clears
the CSSTS bit to 0.
For the transfer using the split transaction, to restart
the next transfer with the S-SPLIT forcibly, set this
bit to 1 through software. However, for the normal
split transaction, this module automatically clears
the CSSTS bit to 0 upon completion of the C-
SPLIT; therefore, clearing the CSSTS bit through
software is not necessary.
Controlling the CSSTS bit through this bit must be
done while UACT is 0 and thus communication is
halted or while no transfer is being performed with
bus disconnection detected.
Setting this bit to 1 while CSSTS is 0 has no effect.
When the function controller function is selected, be
sure to write 0 to this bit.
COMPLETE SPLIT (C-SPLIT) Status of Split
Transaction
Indicates the C-SPLIT status of the split transaction
when the host controller function is selected.
0: START-SPLIT (S-SPLIT) transaction being
processed or the device not using the split
transaction being processed
1: C-SPLIT transaction being processed
This module sets this bit to 1 upon start of the C-
SPLIT and clears this bit to 0 upon detection of C-
SPLIT completion.
When the function controller function is selected,
the read value is invalid.
Rev. 1.00 Nov. 14, 2007 Page 706 of 1262
REJ09B0437-0100