SH7670 Datasheet, PDF (920/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.11 HIF Bank Interrupt Control Register (HIFBICR)
HIFBICR is a 32-bit register that controls HIF bank interrupts. HIFBICR cannot be accessed by an
external device.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0










-



BIE BIF
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 2 
All 0
R
1
BIE
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Bank Interrupt Enable
Enables or disables a bank interrupt request (HIFBI)
issued to the on-chip CPU.
0: HIFBI disabled
1: HIFBI enabled
Rev. 1.00 Nov. 14, 2007 Page 894 of 1262
REJ09B0437-0100