SH7670 Datasheet, PDF (1281/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Index
Numerics
16-bit/32-bit displacement ........................ 39
A
Absolute address....................................... 39
Absolute address accessing....................... 39
Absolute Maximum Ratings ................. 1171
AC Characteristics ................................ 1181
AC Characteristics Measurement
Conditions............................................. 1248
Access size and data alignment .............. 217
Access wait control................................. 229
Accessing MII registers .......................... 430
Address array.................................... 88, 102
Address array read .................................. 102
Address errors......................................... 117
Address map ........................................... 174
Address multiplexing.............................. 235
Address-array write
(associative operation) ............................ 103
Address-array write
(non-associative operation)..................... 102
Addressing modes..................................... 40
Arithmetic operation instructions ............. 59
Auto-refreshing....................................... 262
Auto-request mode ................................. 323
B
Bank active ............................................. 255
Banked register and input
/output of banks ...................................... 162
Bit manipulation instructions.................... 70
Bit synchronous circuit ........................... 870
Branch instructions ................................... 64
Break detection and processing .............. 985
Break on data access cycle.................... 1076
Break on instruction fetch cycle............ 1075
Burst mode.............................................. 336
Burst read................................................ 247
Burst write............................................... 252
Bus format for SSI module ..................... 602
Bus state controller (BSC) ...................... 169
Bus Timing ........................................... 1187
Bus-released state...................................... 73
C
Cache ........................................................ 87
Calculating exception handling
vector table addresses ............................. 112
Canceling software standby mode
(WDT)..................................................... 369
Changing the division ratio ..................... 358
Changing the frequency .................. 357, 369
Changing the multiplication rate............. 357
Clock frequency control circuit............... 345
Clock operating modes ........................... 349
Clock pulse generator (CPG) .................. 343
Clock Timing ........................................ 1182
Clocked synchronous serial format......... 860
CMCNT count timing ............................. 917
Coherency of cache and
external memory ..................................... 101
Compare match timer (CMT) ................. 911
Conditions for determining number of
idle cycles ............................................... 285
Conflict between byte-write and
count-up processes of CMCNT............... 922
Conflict between word-write and
count-up processes of CMCNT............... 921
Conflict between write and
compare-match processes of CMCNT .... 920
Rev. 1.00 Nov. 14, 2007 Page 1255 of 1262
REJ09B0437-0100