SH7616 Datasheet, PDF (97/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.18 B Field ALU Operation Instructions, Multiplication Instructions
Category
Imm. shift
Mnemonic
PSHL #lmm, Dz
PSHA #lmm, Dz
Reserved
Six
operand
parallel
instruction
Three
operand
instructions
PMULS Se, Sf, Dg
Reserved
PSUB Sx, Sy, Du
PMULS Se, Sf, Dg
PADD Sx, Sy, Du
PMULS Se, Sf, Dg
Reserved
PSUBC Sx, Sy, Dz
PADDC Sx, Sy, Dz
PCMP Sx, Sy
Reserved
Reserved
Reserved
PABS Sx, Dz
PRND Sx, Dz
PABS Sy, Dz
PRND Sy, Dz
Reserved
31–27 26
10
25–16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A field 0 0 0 0 0 –16 ≤ lmm ≤ +16
Dz
0 0 0 1 0 – 32 ≤ lmm ≤ +32
00 0 1
00 1
0 1 0 0 Se Sf Sx Sy Dg Du
0 1 0 1 0:X0 0:Y0 0:X0 0:Y0 0:M0 0:X0
1:X1 1:Y1 1:X1 1:Y1 1:M1 1:Y0
0 1 1 0 2:Y0 2:X0 2:A0 2:M0 2:A0 2:A0
3:A1 3:A1 3:A1 3:M1 3:A1 3:A1
01 11
10 0000 0 0
01
10
11
0001
01
10
11
0010
01
10
11
0011
01
10
11
Dz
0: (*¹)
1: (*¹)
2: (*¹)
3: (*¹)
4: (*¹)
5: A1
6: (*¹)
7: A0
8: X0
9: X1
A: Y0
B: Y1
C: M0
D: (*¹)
E: M1
F: (*¹)
Rev. 2.00 Mar 09, 2006 page 71 of 906
REJ09B0292-0200