SH7616 Datasheet, PDF (134/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 3 Oscillator Circuits and Operating Modes
Pin Configuration: Table 3.1 lists the functions relating to the pins relating to the oscillator
circuit.
Table 3.1 Pin Configuration
Pin Name
I/O
CKIO
I/O
XTAL
O
EXTAL
I
CAP1
I
CAP2
I
MD0
I
MD1
I
MD2
I
CKPREQ/CKM I
CKPACK
O
Function
External clock input pin or internal clock output pin
Connects to the crystal resonator
Connects to the crystal resonator or to the external clock input when
using PLL circuit 2
Connects to capacitance for operating PLL circuit 1
Connects to capacitance for operating PLL circuit 2
The level applied to these pins specifies the clock mode
Used as the clock pause request pin, or specifies operation of the crystal
resonator
Clock pause function
PLL Circuit 1: PLL circuit 1 eliminates phase differences between external clocks and clocks
supplied internally within the chip. In high-speed operation, the phase difference between the
reference clocks and operating clocks in the chip directly affects the interface margin with
peripheral devices. On-chip PLL circuit 1 is provided to eliminate this effect.
PLL Circuit 2: PLL circuit 2 either leaves unchanged, doubles, or quadruples the frequency of
clocks provided from the crystal resonator or the EXTAL pin external clock input for the chip
operating frequency. The frequency modification register sets the clock frequency multiplication
factor.
Rev. 2.00 Mar 09, 2006 page 108 of 906
REJ09B0292-0200