SH7616 Datasheet, PDF (117/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
Table 2.30 Single Data Transfer Instructions
Instruction
Operation
Code
Cycles DC Bit
MOVS.W
@-As,Ds
As–2→As,(As)→MSW of
111101AADDDD0000 1
—
Ds,0→LSW of Ds
MOVS.W @As,Ds (As)→MSW of Ds,0→LSW of 111101AADDDD0100 1
—
Ds
MOVS.W
@As+,Ds
(As)→MSW of Ds,0→LSW of 111101AADDDD1000 1
—
Ds, As+2→As
MOVS.W
(As)→MSW of Ds,0→LSW of 111101AADDDD1100 1
—
@As+Ix,Ds
Ds, As+Ix→As
MOVS.W
Ds,@-As
As–2→As,MSW of Ds→(As)* 111101AADDDD0001 1
—
MOVS.W Ds,@As MSW of Ds→(As)*
111101AADDDD0101 1
—
MOVS.W
MSW of Ds→(As)^*,As+2→As 111101AADDDD1001 1
—
Ds,@As+
MOVS.W
MSW of Ds→(As)^*,As+Is→As 111101AADDDD1101 1
—
Ds,@As+Is
MOVS.L
@-As,Ds
As–4→As,(As)→Ds
111101AADDDD0010 1
—
MOVS.L @As,Ds
MOVS.L
@As+,Ds
(As)→Ds
(As)→Ds,As+4→As
111101AADDDD0110 1
—
111101AADDDD1010 1
—
MOVS.L
@As+Is,Ds
(As)→Ds,As+Is→As
111101AADDDD1110 1
—
MOVS.L Ds,
As–4→As,Ds→(As)^*
111101AADDDD0011 1
—
@-As
MOVS.L Ds,@As Ds→(As)^*
MOVS.L
Ds→(As)^*,As+4→As
111101AADDDD0111 1
—
111101AADDDD1011 1
—
Ds,@As+
MOVS.L
Ds,@As+Is
Ds→(As)^*,As+Is→As
111101AADDDD1111 1
—
Note: * When guard bit registers A0G and A1G are specified for the source operand Ds, data is
sign-extended before being transferred.
Rev. 2.00 Mar 09, 2006 page 91 of 906
REJ09B0292-0200