SH7616 Datasheet, PDF (54/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 1 Overview
• Reset State
In this state, the CPU is reset. The reset state is entered when the RES pin goes low. The
power-on reset state is entered if the NMI pin is high, and the manual reset state is entered if
the NMI pin is low.
• Exception Handling State
The exception handling state is a transient state that occurs when the CPU alters the normal
programming flow dues to a reset, interrupt, or other exception handling source.
In the case of a reset, the CPU fetches the execution start address as the initial value of the
program counter (PC) from the exception vector table, and the initial value of the stack pointer
(SP), stores these values, branches to the start address, and begins program execution at that
address.
In the case of an interrupt, etc., the CPU references the SP and saves the PC and status register
(SR) in the stack area. It fetches the start address of the exception service routine from the
exception vector table, branches to that address, and begins program execution.
Subsequently, the processing state is the program execution state.
• Program Execution State
In the program execution state the CPU executes program instructions in normal sequence.
• Power-Down State
In the power-down state the CPU stops operating to conserve power. The power-down state is
entered by executing a SLEEP instruction. The power-down state includes two modes—sleep
mode and standby mode—and a module standby function.
• Bus-Released State
In the bus-released state, the CPU releases the bus to a device that has requested it.
Power-Down State: In addition to the normal program execution state, another CPU processing
state called the power-down state is provided. In this state, CPU operation is halted and power
consumption is reduced. The power-down state includes two modes—sleep mode and standby
mode—and a module standby function.
• Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the standby bit
(SBY) is cleared to 0 in standby control register 1 (SBYCR1). In sleep mode CPU operations
stop but data in the CPU’s internal registers and in on-chip cache memory and on-chip RAM is
retained. The functions of the on-chip supporting modules do not stop.
Rev. 2.00 Mar 09, 2006 page 28 of 906
REJ09B0292-0200