SH7616 Datasheet, PDF (196/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
5.3.13 Vector Number Setting Register G (VCRG)
Vector number setting register G (VCRG) is a 16-bit read/write register that sets the 16-bit timer
pulse unit 0 (TPU0) TCNT0 overflow interrupt vector number (0–127).
VCRG is initialized to H'0000 by a reset. It is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
— TC0VV6 TC0VV5 TC0VV4 TC0VV3 TC0VV2 TC0VV1 TC0VV0
0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 15 and 7 to 0—Reserved: These bits are always read as 0. The write value should always be
0.
Bits 14 to 8—16-Bit Timer pulse unit 0 (TPU0) TCNT0 Overflow Interrupt Vector Number 6 to 0
(TC0VV6–TV0VV0): These bits set the vector number for the 16-bit timer pulse unit 0 (TPU0)
TCNT0 overflow interrupt. There are seven bits, so the value can be set between 0 and 127.
Rev. 2.00 Mar 09, 2006 page 170 of 906
REJ09B0292-0200