SH7616 Datasheet, PDF (382/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
7.11.2 When Using Iφ: Eφ Clock Ratio of 1: 1, 8-Bit Bus Width, and External Wait Input
When using an Iφ: Eφ clock ratio of 1: 1 and an 8-bit bus width, at least 1.5 address hold cycles
should be set.
Set a value other than the initial value in bits AnSHW1, AnSHW0, A4HW1, and A4HW0 for the
relevant space.
7.11.3 When connecting external device to synchronous DRAM
When connecting an external device to the synchronous DRAM, not only CSnN and DACKn but
also other instructions for the synchronous DRAM such as CSnN, RASN, CASN and RDWRN
must be recognized for the estimation of an access sequence.
In some cases, it is difficult to specify read and write cycles only with CSnN and DACKn.
Rev. 2.00 Mar 09, 2006 page 356 of 906
REJ09B0292-0200