SH7616 Datasheet, PDF (632/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
Transmitting
station
Serial communication line
Receiving
station A
(ID = 01)
Receiving
station B
(ID = 02)
Receiving
station C
(ID = 03)
Receiving
station D
(ID = 04)
Serial
data
H'01
(MPB = 1)
H'AA
(MPB = 0)
ID transmission cycle:
Receiving station
specification
Legend
MPB: Multiprocessor bit
Data transmission cycle:
Data transmission
to receiving station
specified by ID
Figure 14.11 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Transmit/Receive Formats: There are four transmit/receive formats. When the multiprocessor
format is specified, the parity bit specification is invalid. For details, see table 14.10.
Clock: See the section on asynchronous mode.
Data Transmit/Receive Operations
• SCI Initialization
See the section on asynchronous mode.
• Multiprocessor Serial Data Transmission
Figure 14.12 shows a sample flowchart for multiprocessor serial data transmission.
Use the following procedure for multiprocessor serial data transmission after enabling the
SCIF for transmission.
Rev. 2.00 Mar 09, 2006 page 606 of 906
REJ09B0292-0200