SH7616 Datasheet, PDF (298/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
• For synchronous DRAM interface
Bit 7: AMX2
Bit 5: AMX1 Bit 4: AMX0
Description
0
0
0
16-Mbit DRAM (1 M × 16 bits),
64-Mbit DRAM (2 M × 32 bits)^*2
1
16-Mbit DRAM (2 M × 8 bits)^*1
1
0
16-Mbit DRAM (4 M × 4 bits)^*1
1
4-Mbit DRAM (256 k × 16 bits)
1
0
0
64-Mbit DRAM (4 M × 16 bits),
128-Mbit DRAM (4 M × 32 bits)^*3
1
64-Mbit DRAM (8 M × 8 bits)^*1,
128-Mbit DRAM (8 M × 16 bits)^*1*4
256-Mbit DRAM (8 M × 32 bits)^*1*4
1
0
Reserved (do not set)
1
2-Mbit DRAM (128 k × 16 bits)
Notes: 1. Reserved. Do not set when SZ bit in MCR is 0 (16-bit bus width).
2. See sction 7.5.11 for the method of connection to a 64-Mbit DRAM with a 2 M × 32-bit
configuration.
3. See figure 7.2 for the method of connection to a 128-Mbit DRAM with a 4 M × 32-bit
configuration.
4. In the case of a 128-Mbit DRAM (8 M × 16-bit), connect to two 128 M bit DRAM
5. s (8 M × 16-bit) by 32-bit data width as Figure2.
5. See figure 7.4 for the method of connection to a 256-Mbit DRAM with an 8 M × 32-bit
configuration.
Rev. 2.00 Mar 09, 2006 page 272 of 906
REJ09B0292-0200