SH7616 Datasheet, PDF (369/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
7.8 Idles between Cycles
Because operating frequencies have become high, when a read from a slow device is completed,
data buffers may not go off in time to prevent data conflicts with the next access. This lowers
device reliability and causes errors. To prevent this, a function has been added to avoid data
conflicts that memorizes the space and read/write state of the preceding access and inserts an idle
cycle in the access cycle for those cases in which problems are found to occur when the next
access starts up. The BSC checks whether a wait is to be inserted in two cases: if a read cycle is
followed immediately by a read access to a different CS space, and if a read access is followed
immediately by a write from the chip. When the chip is writing continuously, the data direction is
always from the chip to other memory, and there are no particular problems. Neither is there any
particular problem if the following read access is to the same CS space, since data is output from
the same data buffer. The number of idle cycles to be inserted into the access cycle when reading
from another CS space, or performing a write, after a read from the CS3 space, is specified by the
IW31 and IW30 bits in WCR1. Likewise, IW21 and IW20 specify the number of idle cycles after
CS2 reads, IW11 and IW10 specify the number after CS1 reads, and IW01 and IW00 specify the
number after CS0 reads. The number of idle cycles after a CS4 read is specified by the IW41 and
IW40 bits in WCR2. From 0, 1, 2, or 4 cycles can be specified. When there is already a gap
between accesses, the number of empty cycles is subtracted from the number of idle cycles before
insertion. When a write cycle is performed immediately after a read access, 1 idle cycle is inserted
even when 0 is specified for waits between access cycles.
When the chip shifts to a read cycle immediately after a write, the write data becomes high
impedance when the clock rises, but the RD signal, which indicates read cycle data output enable,
is not asserted until the clock falls. The result is that no idles are inserted into the cycle.
When bus arbitration is being performed, an empty cycle is inserted for arbitration, so no is
inserted between cycles.
Rev. 2.00 Mar 09, 2006 page 343 of 906
REJ09B0292-0200