SH7616 Datasheet, PDF (689/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
15.4 SIOF Interrupt Sources and DMAC
Each SIOF channel has four interrupt sources: the receive-overrun-error interrupt (RERI0) request,
transmit-underrun-error interrupt (TERI0) request, receive-data-full interrupt/receive-control-data-
register-full interrupt (RDFI0) request, and transmit-data-empty interrupt/transmit-control-data-
register-empty interrupt (TDEI0) request. Table 15.3 shows the interrupt sources and their relative
priorities. The RDFI0 and TDEI0 interrupts are enabled by the RIE, RCIE, TIE, and TCIE bits,
respectively, in SICTR. The RERI0 and TERI0 interrupts cannot be disabled.
An RDFI0 interrupt request is generated when the RDRF bit is set to 1 or the RCD bit is set to 1 in
SISTR.
The DMACE bit should be cleared to 0 in SICTR to have interrupts triggered by both the RDRF
bit and the RCD bit processed by the CPU. In this case the CPU should process interrupts after
reading SISTR and determining which bit triggered them.
Set the DMACE bit to 1 in SICTR to have interrupts triggered by the RDRF bit processed by the
DMAC and interrupts triggered by the RCD bit processed by the CPU. In addition, the priority of
interrupts from SIOF should be set to a high level in order to activate the interrupt controller
(INTC). This will cause interrupts triggered by the RDRF bit to be sent to the DMAC and
interrupts triggered by the RCD bit to be sent to the INTC. The data in SIRDR is read and if the
amount of primary data is less than the setting of bits RFWM3 to RFWM0 in SIFCR, RDRF is
automatically cleared to 0. Interrupts triggered by the RCD bit cannot be processed by the DMAC.
An TDEI0 interrupt request is generated when the TDRE bit is set to 1 or the TCD bit is set to 1 in
SISTR.
The DMACE bit should be cleared to 0 in SICTR to have interrupts triggered by both the TDRE
bit and the TCD bit processed by the CPU. In this case the CPU should process interrupts after
reading SISTR and determining which bit triggered them.
Set the DMACE bit to 1 in SICTR to have interrupts triggered by the TDRE bit processed by the
DMAC and interrupts triggered by the TCD bit processed by the CPU. In addition, the priority of
interrupts from SIOF should be set to a high level in order to activate the INTC. This will cause
interrupts triggered by the TDRE bit to be sent to the DMAC and interrupts triggered by the TCD
bit to be sent to the INTC. The DMAC writes data to SIRDR and if the amount of primary data is
equal to or greater than the setting of bits TFWM3 to TFWM0 in SIFCR, TDRE is automatically
cleared to 0. Interrupts triggered by the TCD bit cannot be processed by the DMAC.
When the RERR bit is set to 1 in SISTR, an RERI0 interrupt request is generated.
When the TERR bit is set to 1 in SISTR, a TERI0 interrupt request is generated.
Rev. 2.00 Mar 09, 2006 page 663 of 906
REJ09B0292-0200