SH7616 Datasheet, PDF (481/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.3.2 Transmission
When the transmitter is enabled and the transmit request bit (TR) is set in the E-DMAC transmit
request register (EDTRR), the E-DMAC reads the descriptor used last time from the transmit
descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start
address register (TDLAR)). If the setting of the TACT bit in the read descriptor is “active,” the E-
DMAC reads transmit frame data sequentially from the transmit buffer start address specified by
TD2, and transfers it to the EtherC. The EtherC creates a transmit frame and starts transmission to
the MII. After DMA transfer of data equivalent to the buffer length specified in the descriptor, the
following processing is carried out according to the TFP value.
1. TFP = 00 or 01 (frame continuation):
Descriptor write-back is performed after DMA transfer.
2. TFP = 01 or 11 (frame end):
Descriptor write-back is performed after completion of frame transmission.
The E-DMAC continues reading descriptors and transmitting frames as long as the setting of the
TACT bit in the read descriptors is “active.” When a descriptor with an “inactive” TACT bit is
read, the E-DMAC resets the transmit request bit (TR) in the transmit register and ends transmit
processing (EDTRR).
Rev. 2.00 Mar 09, 2006 page 455 of 906
REJ09B0292-0200