SH7616 Datasheet, PDF (319/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
Bytes are specified using DQMUU, DQMUL, DQMLU, and DQMLL. The read/write is
performed on the byte whose DQM is low. For 32-bit data, DQMUU specifies 4n address access
and DQMLL specifies 4n + 3 address access. For 16-bit data, only DQMLU and DQMLL are
used. Figure 7.20 shows an example in which a 32-bit connection uses a 256 k × 16 bit
synchronous DRAM. Figure 7.21 shows an example with a 16-bit connection.
Chip
A11
A2
CKIO
CKE
CSn
RAS
CAS/OE
RD/WR
D31
D16
DQMUU/WE3
DQMUL/WE2
D15
D0
DQMLU/WE1
DQMLL/WE0
256 k × 16-bit
synchronous
DRAM
A9
A0
CLK
CKE
CS
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
A9
A0
CLK
CKE
CS
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 7.20 Synchronous DRAM 32-bit Device Connection
Rev. 2.00 Mar 09, 2006 page 293 of 906
REJ09B0292-0200