SH7616 Datasheet, PDF (449/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.2.3 E-DMAC Receive Request Register (EDRRR)
The E-DMAC receive request register issues receive directives to the E-DMAC.
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
RR
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bits 31 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—Receive Request (RR): When 1 is written to this bit, the E-DMAC reads a descriptor, and
then transfers receive data to the buffer in response to receive requests from the EtherC.
Bit 0: RR
Description
0
After frame reception is completed, the receiver is disabled
1
A receive descriptor is read, and transfer is enabled
Notes: In order to receive a frame in response to a receive request, the receive descriptor active
bit in the receive descriptor must be set to “active” beforehand.
1. When the receive request bit is set, the E-DMAC reads the relevant receive descriptor.
2. If the receive descriptor active bit in the descriptor has the “active” setting, the E-DMAC
prepares for a receive request from the EtherC.
3. When one receive buffer of data has been received, the E-DMAC reads the next
descriptor and prepares to receive the next frame. If the receive descriptor active bit in
the descriptor has the “inactive” setting, the RR bit is cleared and operation of the
receive DMAC is halted.
Rev. 2.00 Mar 09, 2006 page 423 of 906
REJ09B0292-0200