SH7616 Datasheet, PDF (205/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 5 Interrupt Controller (INTC)
5.3.22 Vector Number Setting Register P (VCRP)
Vector number setting register P (VCRP) is a 16-bit read/write register that sets the serial I/O with
FIFO (SIOF) receive overrun error interrupt and transmit underrun error interrupt vector numbers
(0–127).
VCRP is initialized to H'0000 by a reset. It is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
— RER0V6 RER0V5 RER0V4 RER0V3 RER0V2 RER0V1 RER0V0
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
— TER0V6 TER0V5 TER0V4 TER0V3 TER0V2 TER0V1 TER0V0
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 14 to 8—Serial I/O with FIFO (SIOF) Receive Overrun Error Interrupt Vector Number 6 to 0
(RER0V6–RER0V0): These bits set the vector number for the serial I/O with FIFO (SIOF) receive
overrun error interrupt. There are seven bits, so the value can be set between 0 and 127.
Bits 6 to 0—Serial I/O with FIFO (SIOF) Transmit Underrun Error Interrupt Vector Number 6 to
0 (TER0V6–TER0V0): These bits set the vector number for the serial I/O with FIFO (SIOF)
transmit underrun error interrupt. There are seven bits, so the value can be set between 0 and 127.
Rev. 2.00 Mar 09, 2006 page 179 of 906
REJ09B0292-0200