SH7616 Datasheet, PDF (355/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
CKIO
Tp
Tr
Tc1
Tw
Twx
Tc2
A24–A16
A15–A1
RAS
CASn
RD/WR
Read RD
D31–D0
RD/WR
Write _RD
D31–D0
DACKn*
WAIT
Note: * DACKn waveform when active-low is specified
Figure 7.42 External Wait State Timing
7.6.5 Burst Access
In addition to the ordinary mode of DRAM access, in which row addresses are output at every
access and data is then accessed, DRAM also has a high-speed page mode for use when
continuously accessing the same row that enables fast access of data by changing only the column
address after the row address is output. Select ordinary access or high-speed page mode by setting
Rev. 2.00 Mar 09, 2006 page 329 of 906
REJ09B0292-0200