SH7616 Datasheet, PDF (615/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
14.2.12 FIFO Error Register (SCFER)
The FIFO error register (SCFER) indicates the data location at which a parity error or framing
error occurred in receive data stored in the receive FIFO data register (SCFRDR).
SCFER can be read at all times.
Upper 8 bits: 15
14
13
12
11
10
9
8
ED15 ED14 ED13 ED12 ED11 ED10 ED9
ED8
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Lower 8 bits: 7
6
5
4
3
2
1
0
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 15 to 0—Error Data Flags 15 to 0 (ED15 to ED0): These flags indicate the data location in the
receive FIFO data register at which an error occurred. When data in the nth stage of the buffer
contains an error, the nth bit is set to 1. Note that this register is not cleared by setting the RFRST
bit to 1 in SCFCR.
Bits 15 to 0:
ED15 to ED0
Description
0
No parity or framing error in data in corresponding stage of register FIFO
(Initial value)
1
Parity or framing error present in data in corresponding stage of register FIFO
Note: A reset operation is performed in the event of a reset, when the module standby function is
used, or in standby mode. These flags are also cleared by reading the data in which the
parity error or framing error occurred from SCFRDR.
14.2.13 IrDA Mode Register (SCIMR)
The IrDA mode register (SCIFMR) allows selection of the IrDA mode and the IrDA output pulse
width, and inversion of the IrDA receive data polarity.
SCIMR can be read and written to at all times.
SCIMR is initialized to H'00 by a reset, by the module standby function, and inop standby mode.
Rev. 2.00 Mar 09, 2006 page 589 of 906
REJ09B0292-0200