SH7616 Datasheet, PDF (506/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
External Request Mode: In this mode a transfer is started by a transfer request signal (DREQn)
from an external device. Choose one of the modes shown in table 11.4 according to the application
system. When DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer
is performed upon input of a DREQn signal.
Table 11.4 Selecting External Request Modes with the TA and AM Bits
CHCR
TA AM
00
1
Transfer
Address Mode
Dual address
mode
Dual address
mode
Acknowledge Mode
DACKn output in read
cycle
DACKn output in write
cycle
Source
Any^*
Any^*
Destination
Any^*
Any^*
10
Single address
mode
Data transferred from
memory to device
External memory or External device
memory-mapped with DACK
external device
1 Single address Data transferred from External device
mode
device to memory
with DACK
External memory or
memory-mapped
external device
Note: * External memory, memory-mapped external device, and on-chip peripheral module
(excluding DMAC, BSC, UBC, cache memory, E-DMAC, and EtherC).
Choose to detect DREQn either by the falling edge or by level using the DS and DL bits in
CHCR0 and CHCR1 (DS = 0 is level detection, DS = 1 is edge detection; DL = 0 is active-low,
DL = 1 is active-high). The source of the transfer request does not have to be the data transfer
source or destination.
When 0 (level detection) is set to the DS bit of CHCR0 and CHCR1, set the TB bit to 0 (cycle-
steal mode) and set the TS1 and TS0 bits of CHCR0 and CHCR1 to either 00 (byte unit), 01 (word
unit), or 10 (long word unit).
When 0 is set to the DS bit of CHCR0 and CHCR1, when 1 (burst mode) is set to the TB bit of
CHCR0 and CHCR1, and when 11 (16 byte unit) is set to the TS1 and TS0 bits of CHCR1 and
CHCR1, operation is not guaranteed.
Rev. 2.00 Mar 09, 2006 page 480 of 906
REJ09B0292-0200