SH7616 Datasheet, PDF (81/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

PC relative
addressing
Immediate
addressing
disp:8
disp:12
Rn
#imm:8
#imm:8
#imm:8
Section 2 CPU
The effective address is the PC value sign-extended PC + disp × 2
with an 8-bit displacement (disp), doubled, and
added to the PC value
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
The effective address is the PC value sign-extended PC + disp × 2
with a 12-bit displacement (disp), doubled, and
added to the PC value
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
The effective address is the register PC value plus
Rn
PC + Rn
PC
+
PC + Rn
Rn
The 8-bit immediate data (imm) for the TST, AND, —
OR, and XOR instructions are zero-extended
The 8-bit immediate data (imm) for the MOV, ADD, —
and CMP/EQ instructions are sign-extended
The 8-bit immediate data (imm) for the TRAPA
—
instruction is zero-extended and is quadrupled
Rev. 2.00 Mar 09, 2006 page 55 of 906
REJ09B0292-0200