SH7616 Datasheet, PDF (262/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.3 Operation
6.3.1 User Break Operation Sequence
The sequence of operations from setting of break conditions to user break interrupt exception
handling is described below.
1. Set the break address in the break address register (BARA/BARB/BARC/BARD), the bits to
be masked in the break address mask register (BAMRA/BAMRB/BAMRC/BAMRD), the
break bits in the break data register (BDRC/BDRD), and the data to be masked in the break
data mask register (BDMRC/BDMRD).
Set the break bus conditions in the break bus cycle register (BBRA/BBRB/BBRC/BBRD).
Make three settings—CPU cycle/on-chip DMAC cycle select, instruction fetch/data access
select, and read/write select—for each of BBRA, BBRB, BBRC, and BBRD. A user break
interrupt will not be generated for a channel for which any one of these settings is 00.
Set the respective conditions in the corresponding BRCR register bits.
2. When a set condition is satisfied, the UBC sends a user break interrupt request to the interrupt
controller (INTC). The CPU condition match flag (CMFCA/CMFCB/CMFCC/CMFCD) and
DMAC condition match flag (CMFPA/CMFPB/CMFPC/CMFPD) is also set for the matched
condition for the respective channel.
3. The INTC determines the priority of the user break interrupt. As the priority level of a user
break interrupt is 15, the interrupt is accepted if the level set in the interrupt mask bits (I3 to I0)
in the status register (SR) is 14 or less. If the level set in bits I3 to I0 is 15, the user break
interrupt is not accepted, but is held pending until it can be. For details of priority
determination, see section 5, Interrupt Controller (INTC).
4. If the user break interrupt is accepted after its priority is determined, the CPU begins user
break interrupt exception handling.
5. Whether a set condition is matched or not can be ascertained from the respective condition
match flag (CMFCA, CMFPA, CMFCB, CMFPB, CMFCC, CMFPC, CMFCD, or CMFPD).
These flags are set by a match with the set condition, but are not reset. Therefore, if the setting
of a particular flag is to be checked again, the flag must be cleared by writing 0.
When an execution-times break is specified for channel C or D, the CMFCC, CMFPC,
CMFCD, or CMFPD flag is set when the number of executions matches the number of
executions specified by BETRC or BETRD.
Rev. 2.00 Mar 09, 2006 page 236 of 906
REJ09B0292-0200