SH7616 Datasheet, PDF (827/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

21.2 Register Descriptions
Section 21 Power-Down Modes
21.2.1 Standby Control Register 1 (SBYCR1)
Bit: 7
6
5
4
3
2
1
0
SBY
HIZ MSTP5 MSTP4 MSTP3 — MSTP1 —
(UBC) (DMAC) (DSP)
(FRT)
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R
R/W
R
Standby control register 1 (SBYCR1) is an 8-bit read/write register that sets the power-down
mode. SBYCR is initialized to H'00 by a reset.
Bit 7—Standby (SBY): Specifies transition to standby mode. To enter the standby mode, halt the
WDT (set the TME bit in WTCSR to 0) and set the SBY bit.
Bit 7: SBY
0
1
Description
Executing a SLEEP instruction puts the chip into sleep mode
Executing a SLEEP instruction puts the chip into standby mode
(Initial value)
Bit 6—Port High Impedance (HIZ): Selects whether output pins are set to high impedance or
retain the output state in standby mode. When HIZ = 0 (initial state), the specified pin retains its
output state. When HIZ = 1, the pin goes to the high-impedance state. See Appendix B.1, Pin
States during Resets, Power-Down States and Bus Release State, for which pins are controlled.
Bit 6: HIZ
0
1
Description
Pin state retained in standby mode
Pin goes to high impedance in standby mode
(Initial value)
Bit 5—Module Stop 5 (MSTP5): Specifies halting the clock supply to the user break controller
(UBC). When the MSTP5 bit is set to 1, the supply of the clock to the UBC is halted. When the
clock halts, the UBC registers retain their pre-halt state. Do not set this bit while the UBC is
running.
Bit 5: MSTP5
0
1
Description
UBC running
Clock supply to UBC halted
(Initial value)
Rev. 2.00 Mar 09, 2006 page 801 of 906
REJ09B0292-0200