SH7616 Datasheet, PDF (425/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 9 Ethernet Controller (EtherC)
9.2.18 Too-Long Frame Receive Counter Register (TLFRCR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
TLFC15 TLFC14 TLFC13 TLFC12 TLFC11 TLFC10
Initial value: 0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
9
TLFC9
0
R/W
8
TLFC8
0
R/W
Bit:
Initial value:
R/W:
7
TLFC7
0
R/W
6
TLFC6
0
R/W
5
TLFC5
0
R/W
4
TLFC4
0
R/W
3
TLFC3
0
R/W
2
TLFC2
0
R/W
1
TLFC1
0
R/W
0
TLFC0
0
R/W
TLFRCR is a 16-bit counter that indicates the number of frames received with a length exceeding
the value specified by the receive frame length register (RFLR). When the value in this register
reaches H'FFFF (65,535), the count is halted. The counter value is cleared to 0 by a write to this
register (the write value is immaterial).
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—Too-Long Frame Receive Count 15 to 0 (TLFC15 to TLFC0): These bits indicate
the count of frames received with a length exceeding the value in RFLR.
Notes: If the value specified by RFLR is 1518 bytes, TLFRCR is incremented by reception of a
frame with a length of 1519 bytes or more.
TLFRCR is not incremented when a frame containing residual bits is received. In this
case, the reception of the frame is indicated in the residual-bit frame counter register
(RFCR).
Rev. 2.00 Mar 09, 2006 page 399 of 906
REJ09B0292-0200