SH7616 Datasheet, PDF (832/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 21 Power-Down Modes
Table 21.3 Register States in Standby Mode
Module
Interrupt controller (INTC)
User break controller (UBC)
Bus state controller (BSC)
Direct memory access
controller (DMAC)
Watchdog timer (WDT)
16-bit free-running timer (FRT)
Serial communication interface
with FIFO (SCIF1–2)
Serial I/O with FIFO (SIOF)
Serial I/O (SIO1–2)
User debug interface
(H-UDI)
16-bit timer pulse unit (TPU)
Pin function controller (PFC)
Ethernet controller direct
memory access controller (E-
DMAC)
Ethernet controller (EtherC)
Others
Registers Initialized
—
—
—
DMA channel control
register 0, 1
DMA operation register
Bits 7–5 of the timer
control/status register
Reset control/status
register
All registers
All registers
—
—
—
—
—
All registers
All registers
—
Registers
Registers that Retain with Undefined
Data
Contents
All registers
—
All registers
—
All registers
—
• DMA source
—
address registers 0
and 1
• DMA destination
address registers 0
and 1
• DMA transfer count
registers 0 and 1
• DMA request/
response selection
control registers 0
and 1
• Vector number
setting registers
DMA0 and DMA1
Bits 2–0 of the timer —
control/status register
Timer counter
—
—
—
—
All registers
—
All registers
—
All registers
—
All registers
—
All registers
—
—
—
—
—
Standby control register —
1, 2
Frequency modification
register
Rev. 2.00 Mar 09, 2006 page 806 of 906
REJ09B0292-0200