SH7616 Datasheet, PDF (136/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 3 Oscillator Circuits and Operating Modes
Clock Mode
5
6
Function/Operation
Clock Source
Only PLL circuit 1 operates. Operate PLL circuit 1 when
operating with a 1/4 φ cycle lag of the clock input from the
CKIO pin and the internal clocks (Iφ, Eφ, Pφ) with respect to
system clock φ. PLL circuit 2 does not operate in this mode
PLL circuit 1 can be switched between the operating and
halted states by means of control bits in the frequency
modification register (FMR). However, clock phase shifting is
not performed when PLL circuit 1 is halted.
External clock input
Normally, mode 4 should be used.
PLL circuits 1 and 2 do not operate. Set this mode when a
clock having a frequency equal to that of clocks the clock
input from the CKIO pin is used
The internal clock frequency can be changed in each clock mode (see section 3.2.5, Operating
Frequency Selection by Register).
In clock modes 4 to 6, the frequency of the clock input from the CKIO pin can be changed, or the
clock can be stopped (see section 21.4.4, Clock Pause Function).
Table 3.3 lists the relationship between pins MD2 to MD0 and the clock operating mode. Do not
switch the MD2–MD0 pins while they are operating. Switching will cause operating errors.
Rev. 2.00 Mar 09, 2006 page 110 of 906
REJ09B0292-0200