SH7616 Datasheet, PDF (237/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.2.7 Break Address Register C (BARC)
BARCH
Bit:
Initial value:
R/W:
15
BAC31
0
R/W
14
BAC30
0
R/W
13
BAC29
0
R/W
12
BAC28
0
R/W
11
BAC27
0
R/W
10
BAC26
0
R/W
9
BAC25
0
R/W
8
BAC24
0
R/W
Bit:
Initial value:
R/W:
7
BAC23
0
R/W
6
BAC22
0
R/W
5
BAC21
0
R/W
4
BAC20
0
R/W
3
BAC19
0
R/W
2
BAC18
0
R/W
1
BAC17
0
R/W
0
BAC16
0
R/W
BARCL
Bit:
Initial value:
R/W:
15
BAC15
0
R/W
14
BAC14
0
R/W
13
BAC13
0
R/W
12
BAC12
0
R/W
11
BAC11
0
R/W
10
BAC10
0
R/W
9
BAC9
0
R/W
8
BAC8
0
R/W
Bit:
Initial value:
R/W:
7
BAC7
0
R/W
6
BAC6
0
R/W
5
BAC5
0
R/W
4
BAC4
0
R/W
3
BAC3
0
R/W
2
BAC2
0
R/W
1
BAC1
0
R/W
0
BAC0
0
R/W
Break address register C (BARC) consists of two 16-bit readable/writable registers: break address
register CH (BARCH) and break address register CL (BARCL). BARCH specifies the upper half
(bits 31 to 16) of the address used as a channel C break condition, and BARCL specifies the lower
half (bits 15 to 0). The address bus connected to the X/Y memory can also be specified as a break
condition by making a setting in the XYEC bit/XYSC bit in break bus cycle register C (BBRC).
When XYEC = 0, BAC31 to BAC0 specify the address. When XYEC = 1, the upper 16 bits
(BAC31 to BAC16) of BARC specify the X address bus, and the lower 16 bits (BAC15 to BAC0)
specify the Y address bus. BARCH and BARCL are initialized to H'0000 by a power-on reset;
after a manual reset, their values are undefined.
Rev. 2.00 Mar 09, 2006 page 211 of 906
REJ09B0292-0200