SH7616 Datasheet, PDF (680/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 15 Serial I/O with FIFO (SIOF)
15.3 Operation
15.3.1 Input when TRMD = 0 in SIFCR
Figure 15.2 shows interval transfer mode (SE set to 1 in SICTR) with MSB first (LM cleared to 0
in SIFCR).
Figure 15.3 shows continuous transfer mode (SE cleared to 0 in SICTR) with MSB first (LM
cleared to 0 in SIFCR).
Set to 1 when an amount of data
equal to or greater than the setting of
bits RFWM3 to RFWM0 in SIFCR is
received
RDRF
Synchronous internal clock
SIRDR
A[7:0]
SIRSR
Undefined
A[7] A[7:6]
A[7:1]
A[7:0]
B[7]
SRCK
SRS
SRXD
A[7] A[6] A[5]
A[0]
Invalid
B[7] B[6]
Note: DL = 0: 8-bit data transfer
SE = 1: Synchronous transfer in start signal mode
LM = 0: MSB first
TRMD = 0: LSB of transmitted primary data is value in SITDR
Figure 15.2 Reception: Interval Transfer Mode/MSB First
Rev. 2.00 Mar 09, 2006 page 654 of 906
REJ09B0292-0200