SH7616 Datasheet, PDF (250/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
specifies which bits of the break data set in BDRDH are to be masked, and BDMRDL specifies
which bits of the break data set in BDRDL are to be masked. Operation also depends on bits
XYED and XYSD in BBRD as shown below. BDMRDH and BDMRDL are initialized to H'0000
by a power-on reset; after a manual reset, their values are undefined.
BDMRD Configuration
XYED = 0
XYED = 1
Data
X data
(when XYSD = 0)
Y data
(when XYSD = 1)
Upper 16 Bits
(BDMD31 to BDMD16)
Upper 16 bits maskable
Maskable
—
Lower 16 Bits
(BDMD15 to BDMD0)
Lower 16 bits maskable
—
Maskable
Bit 31 to 0:
BDMDn
Description
0
Channel D break data bit BDDn is included in break condition (Initial value)
1
Channel D break data bit BDDn is masked, and not included in condition
Notes: 1. n = 31 to 0
2. When including the data bus value in the break condition, specify the operand size.
3. When specifying byte size, and using odd-address data as a break condition, set the
value in bits 7 to 0 of BDRD and BDMRD. When using even-address data as a break
condition, set the value in bits 15 to 8. The unused 8 bits of these registers have no
effect on the break condition.
Rev. 2.00 Mar 09, 2006 page 224 of 906
REJ09B0292-0200