SH7616 Datasheet, PDF (294/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
Bits 7 to 0—Area 3 to 0 CSn Assert Period Extension (A3SHW1–A0SHW0): These bits specify
the number of cycles from address/CSn output to RD/WEn assertion and from RD/WEn negation
to address/CSn hold for areas 3 to 0.
A3SHW1
A2SHW1
A1SHW1
A0SHW1
0
1
Note: * n = 0 to 3
A3SHW0
A2SHW0
A1SHW0
A0SHW0
0
1
0
1
Description
0.5 cycle, CSn^* hold cycle = 0 cycles
1.5 cycle, CSn^* hold cycle = 1 cycle
2.5 cycle, CSn^* hold cycle = 2 cycles
Reserved (do not set)
(Initial value)
7.2.7 Individual Memory Control Register (MCR)
Bit: 15
14
13
12
11
10
TRP0 RCD0 TRWL0 TRAS1 TRAS0 BE
Initial value: 0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W
9
RASD
0
R/W
8
TRWL1
0
R/W
Bit: 7
6
5
4
3
2
1
0
AMX2 SZ AMX1 AMX0 RFSH RMODE TRP1 RCD1
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The TRP1–TRP0, RCD1–RCD0, TRWL1–TRWL0, TRAS1–TRAS0, BE, RASD, AMX2–AMX0
and SZ bits are initialized after a power-on reset. Do not write to them thereafter. When writing to
them, write the same values as they are initialized to. Do not access CS2 or CS3 until register
initialization is completed.
Bits 1 and 15—RAS Precharge Time (TRP1, TRP0): When DRAM is connected, specifies the
minimum number of cycles after RAS is negated before the next assert. When synchronous
DRAM is connected, specifies the minimum number of cycles after precharge until a bank active
command is output. See section 7.5, Synchronous DRAM Interface, for details.
Rev. 2.00 Mar 09, 2006 page 268 of 906
REJ09B0292-0200