SH7616 Datasheet, PDF (593/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 14 Serial Communication Interface with FIFO (SCIF)
For the relationship between the clock source, the bit rate register setting, and the baud rate, see
section 14.2.9, Bit Rate Register (SCBRR).
Bit 1:
CKS1
Bit 0:
CKS0
Description
0
0
Pφ clock
1
Pφ/4 clock
1
0
Pφ/16 clock
1
Pφ/64 clock
Note: Pφ = peripheral clock
(Initial value)
14.2.6 Serial Control Register (SCSCR)
Bit: 7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
—
CKE1 CKE0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
The serial control register (SCSCR) performs enabling or disabling of SCIF transmit/receive
operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the
transmit/receive clock source.
SCSCR can be read or written to by the CPU at all times.
SCSCR is initialized to H'00 by a reset, by the module standby function, and in standby mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt
(TXI) request generation when, after serial transmit data is transferred from the transmit FIFO data
register (SCFTDR) to the transmit shift register (SCTSR), the number of data bytes in SCFTDR
falls to or below the transmit trigger set number, and the TDFE flag is set to 1 in the serial status 1
register (SC1SSR).
Bit 7: TIE
Description
0
Transmit-FIFO-data-empty interrupt (TXI) request disabled^*
(Initial value)
1
Transmit-FIFO-data-empty interrupt (TXI) request enabled
Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger
set number to SCFTDR, reading 1 from the TDFE flag, then clearing it to 0, or by clearing
the TIE bit to 0. When transmit data is written to SCFTDR using the on-chip DMAC, the
TDFE flag is cleared automatically.
Rev. 2.00 Mar 09, 2006 page 567 of 906
REJ09B0292-0200