SH7616 Datasheet, PDF (653/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Start bit
Section 14 Serial Communication Interface with FIFO (SCIF)
UART frame
Data
Stop bit
0 1 0 1 0 01 1 0 1
Transmission
Start bit
Reception
IR frame
Data
Stop bit
01
01
0 01 1
01
Bit cycle
3/16 bit cycle
pulse width
Figure 14.24 IrDA Mode Transmit/Receive Operations
Pulse Width Selection: In transmission, the IR frame pulse width can be selected as either 3/16 of
the transmission bit rate or a smaller pulse width by means of the PSEL bit in the IrDA mode
register (SCIMR).
The SCIF includes a baud rate generator that generates the transmit frame bit rate and a baud rate
generator that generates the IRCLK signal for varying the pulse width.
When the PSEL bit is cleared to 0 in SCIMR, a width of 3/16 the bit rate set in the bit rate register
(SCBRR) is output as the IR frame pulse width. As the pulse width is the direct infrared emission
time; if the user wishes to minimize the pulse width in order to reduce power consumption, the
PSEL bit should be set to 1 in SCIMR and a setting should also be made in bits ICK3 to ICK0 in
the serial mode register (SCSMR) to generate the IRCLK signal, resulting in output with the
minimum settable pulse width.
Rev. 2.00 Mar 09, 2006 page 627 of 906
REJ09B0292-0200