SH7616 Datasheet, PDF (256/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
Bit 18—PC Break Select B (PCBB): Selects whether a channel B instruction fetch cycle break is
effected before or after execution of the instruction.
Bit 18: PCBB
0
1
Description
Channel B instruction fetch cycle break is effected before instruction execution
(Initial value)
Channel B instruction fetch cycle break is effected after instruction execution
Bits 17 and 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 15—CPU Condition Match Flag C (CMFCC): This flag is set to 1 when a CPU bus cycle
condition, among the break conditions set for channel C, is satisfied. This flag is not cleared to 0
(if the flag setting is to be checked again after it has once been set, the flag must be cleared by a
write).
Bit 15: CMFCC
0
1
Description
User break interrupt has not been generated by a channel C CPU cycle
condition
(Initial value)
User break interrupt has been generated by a channel C CPU cycle condition
Bit 14—DMAC Condition Match Flag C (CMFPC): This flag is set to 1 when an on-chip DMAC
bus cycle condition, among the break conditions set for channel C, is satisfied. This flag is not
cleared to 0 (if the flag setting is to be checked again after it has once been set, the flag must be
cleared by a write).
Bit 14: CMFPC
0
1
Description
User break interrupt has not been generated by a channel C on-chip DMAC
cycle condition
(Initial value)
User break interrupt has been generated by a channel C on-chip DMAC cycle
condition
Bit 13—Execution-Times Break Enable C (ETBEC): Enables a channel C execution-times break
condition. When this bit is 1, a user break interrupt is generated when the number of break
conditions that have occurred equals the number of executions specified by the break execution
times register (BETRC).
Bit 13: ETBEC
0
1
Description
Channel C execution-times break condition is disabled
Channel C execution-times break condition is enabled
(Initial value)
Rev. 2.00 Mar 09, 2006 page 230 of 906
REJ09B0292-0200