SH7616 Datasheet, PDF (495/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 11 Direct Memory Access Controller (DMAC)
Bits 11 and 10—Transfer Size Bits (TS1, TS0): Select the DMA transfer size. When 11 is set to
bits TS1 and TS0 (in the 16-byte unit), request mode is available only in auto-request mode and at
edge detection in external request mode. When 11 is set to bits TS1 and TS0 (in the 16-byte unit)
and level detection in external request mode and internal peripheral-module request mode are set,
system operations are not guaranteed. TS1 and TS0 are initialized to 00 by a reset and in standby
mode. Values are retained during a module standby.
Bit 11: TS1
Bit 10: TS0
Description
0
0
Byte unit^*
(initial value)
1
Word (2-byte) unit
1
0
Longword (4-byte) unit
1
16-byte unit (4 longword transfers)
Note: * The byte unit setting should not be used if a destination address has been set in internal
memory for the dual address mode.
Bit 9—Auto Request Mode Bit (AR): Selects either auto-request mode (in which transfer requests
are generated automatically within the DMAC) or a mode using external requests or requests from
on-chip peripheral modules (SCIF, TPU, SIOF, SIO). The AR bit is initialized to 0 by a reset and
in standby mode. Its value is retained during a module standby.
Bit 9: AR
0
1
Description
External/on-chip peripheral module request mode
Auto-request mode
(Initial value)
Bit 8—Acknowledge/Transfer Mode Bit (AM): In dual address mode, this bit selects whether the
DACKn signal is output during the data read cycle or write cycle. In single-address mode, it
selects whether to transfer data from memory to device or from device to memory. The AM bit is
initialized to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 8: AM
0
1
Description
DACKn output in read cycle (dual address mode)/transfer from memory
to device (single address mode)
(Initial value)
DACKn output in write cycle (dual address mode)/transfer from device
to memory (single address mode)
Rev. 2.00 Mar 09, 2006 page 469 of 906
REJ09B0292-0200