SH7616 Datasheet, PDF (131/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 2 CPU
2.6 Usage Notes
2.6.1 When not using DSP instructions
When DSP instructions are not used, execute the following dummy instruction in the initialization
section of application software in order to reduce the operating current.
PCLR
A0 : Clear the A0 register.
PSHA #5, A0 : 5 bit shift to left.
2.6.2
When executing a combination of double-precision multiplication or double-
precision product-sum operation (CPU instruction) and DSP computing
instruction
When double-precision multiplication (MUL.L, DMULU.L, DMULS.L) or double-precision
product-sum operation (MAC.L) in CPU instructions is executed in combination with DSP
computing instruction (when the following conditions 1 and 2 are met simultaneously), a
malfunction may occur in the instructions indicated in 2-b.
1. Execution of instructions from the internal memory or cache.
2. Execution of the following instruction strings in the order of a, b and c.
a. Double-precision multiplication (MUL.L, DMULU.L, DMULS.L) or double-precision
product-sum operation (MAC.L)
b. DSP computing instruction excluding PMULS, PSTS and PLDS
c. Execution of PMLS, PSTS or PLDS instruction
The above caution also applies when there is a delayed jump instruction immediately before the
above 2-a, and the instruction 2-a is in a delayed slot, and the instructions 2-b and 2-c are
described continuously at the jump destination.
To prevent the malfunction, take one of the following measures.
1 Do not execute the instruction string described in the above condition 2.
2. When the instruction string described in the above condition 2 exists on the instruction code
and if no problem is caused by switching instructions b and c, switch the locations of
instructions b and c.
3. When the instruction string described in the above condition 2 exists on the instruction code
and if a problem is caused by switching instructions b and c, insert one or more NOP
instructions or CPU instructions that are not related to the multiplier.
Rev. 2.00 Mar 09, 2006 page 105 of 906
REJ09B0292-0200