SH7616 Datasheet, PDF (350/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
7.6 DRAM Interface
7.6.1 DRAM Direct Connection
When the DRAM and other memory enable bits (DRAM2–DRAM0) in BCR1 are set to 010, the
CS3 space becomes DRAM space, and a DRAM interface function can be used to directly connect
DRAM.
The data width of an interface can be 16 or 32 bits (figures 7.38 and 7.39). Two-CAS 16-bit
DRAMs can be connected, since CAS is used to control byte access. The RAS, CAS3–CAS0, and
RD/WR signals are used to connect the DRAM. When the data width is 16 bits, CAS3, and CAS2
are not used. In addition to ordinary read and write access, burst access using high-speed page
mode is also supported.
Chip
A10
A2
256 k × 16-bit
DRAM
A8
A0
RAS
RD/WR
D31
D16
CAS3
CAS2
D15
D0
CAS1
CAS0
RAS
OE
WE
I/O15
I/O0
UCAS
LCAS
A8
A0
RAS
OE
WE
I/O15
I/O0
UCAS
LCAS
Figure 7.38 Example of DRAM Connection (32-Bit Data Width)
Rev. 2.00 Mar 09, 2006 page 324 of 906
REJ09B0292-0200