SH7616 Datasheet, PDF (575/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

Section 13 Watchdog Timer (WDT)
13.2.4 Notes on Register Access
The watchdog timer’s WTCNT, WTCSR, and RSTCSR registers differ from other registers in that
they are more difficult to write. The procedures for writing and reading these registers are given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by byte or longword transfer instructions. WTCNT and
WTCSR both have the same write address. The write data must be contained in the lower byte of
the written word. The upper byte must be H'5A (for WTCNT) or H'A5 (for WTCSR) (figure 13.2).
This transfers the write data from the lower byte to WTCNT or WTCSR.
Writing to WTCNT
Address:
H'FFFFFE80
15
H'5A
87
0
Write data
Writing to WTCSR
Address:
H'FFFFFE80
15
H'A5
87
0
Write data
Figure 13.2 Writing to WTCNT and WTCSR
Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFFFE82. It
cannot be written by byte or longword transfer instructions. Procedures for writing 0 in WOVF
(bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 13.3. To
write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte.
This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE
and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values
of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The
WOVF bit is not affected.
Rev. 2.00 Mar 09, 2006 page 549 of 906
REJ09B0292-0200