SH7616 Datasheet, PDF (19/935 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

10.2.10 Transmit FIFO Threshold Register (TFTR)......................................................... 439
10.2.11 FIFO Depth Register (FDR)................................................................................. 441
10.2.12 Receiver Control Register (RCR) ........................................................................ 442
10.2.13 E-DMAC Operation Control Register (EDOCR) ................................................ 443
10.2.14 Receiving-Buffer Write Address Register (RBWAR) ......................................... 444
10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) .................................... 445
10.2.16 Transmission-Buffer Read Address Register (TBRAR) ...................................... 446
10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................... 447
10.3 Operation........................................................................................................................... 448
10.3.1 Descriptor List and Data Buffers ......................................................................... 448
10.3.2 Transmission ........................................................................................................ 455
10.3.3 Reception ............................................................................................................. 457
10.3.4 Multi-Buffer Frame Transmit/Receive Processing .............................................. 459
Section 11 Direct Memory Access Controller (DMAC).......................................... 461
11.1 Overview........................................................................................................................... 461
11.1.1 Features ................................................................................................................ 461
11.1.2 Block Diagram ..................................................................................................... 463
11.1.3 Pin Configuration................................................................................................. 464
11.1.4 Register Configuration......................................................................................... 465
11.2 Register Descriptions ........................................................................................................ 466
11.2.1 DMA Source Address Registers 0 and 1 (SAR0, SAR1)..................................... 466
11.2.2 DMA Destination Address Registers 0 and 1 (DAR0, DAR1) ............................ 466
11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0, TCR1) ..................................... 467
11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0, CHCR1) ............................. 467
11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1) ................. 472
11.2.6 DMA Request/Response Selection Control Registers 0 and 1
(DRCR0, DRCR1) ............................................................................................... 473
11.2.7 DMA Operation Register (DMAOR)................................................................... 475
11.3 Operation........................................................................................................................... 477
11.3.1 DMA Transfer Flow............................................................................................. 477
11.3.2 DMA Transfer Requests ...................................................................................... 479
11.3.3 Channel Priorities................................................................................................. 483
11.3.4 DMA Transfer Types ........................................................................................... 486
11.3.5 Number of Bus Cycles ......................................................................................... 496
11.3.6 DMA Transfer Request Acknowledge Signal Output Timing ............................. 496
11.3.7 DREQn Pin Input Detection Timing.................................................................... 507
11.3.8 DMA Transfer End .............................................................................................. 513
11.3.9 BH Pin Output Timing......................................................................................... 514
11.4 Usage Examples................................................................................................................ 516
Rev. 2.00 Mar 09, 2006 page xix of xxvi